0.5.1 has been released

To do for 0.5.1

  • solve bug with right shifting of negative numbers - use arithmetic shift in Verilog
  • solve inconsistency bug with Python versions in


  • review shortcutting boolean operations, may be too restrictive
  • use if instead of case with a single test
  • document undocumented feature to hide MyHDL code from the Verilog convertor, using "if __debug__"

To do for 0.5

User-defined Verilog: error handling

  • acceptable values of the driven attribute
  • error messages when exceptions occur with user-defined code
  • __toVerilog__ not supported in generator functions

Signed arithmetic:

  • investigate fine-grained approach
  • use base classes for Enum and EnumItem, so that type-checking is possible


  • check typo bug with signal tracing
  • check simulation suspend mechanism


  • investigate approach to remove limitations on @always decorator
  • infer specialized _Waiter class depending on sensitivity list

Verification and error reporting:

  • argument tests on @always
  • test waiter inference for @always and @always_comb
  • argument tests on @instance

Get feedback on style issues

  • clk.posedge instead of posedge(clk)
  • promoting general usage of decorators

Update documentation ...

  • update what's new document
  • add note on positive numbers returned by slicing of intbv
  • make full pass over manual with new info