MyHDL Project Introduction
MyHDL is a Python package that extends Python as a hardware description language (HDL). MyHDL empowers implementation of complex digital circuits that can be targeted towards ASIC and FPGA technologies.
Jan Decaluwe is the creator and BDFL. The MyHDL project has been around for many years and has had many successes bringing a modern and software influenced approach to HDL development. MyHDL has been used for various FPGA projects and numerous ASIC projects 1.
The following are good starting points to learn more about MyHDL:
Questions can also be posted to:
The gitter channel is informal and typically a question will be part of a time-limited conversation. On the forum more users/developers will have a chance to comment on the question and the question will receive more feedback over time.
Before a question is posted to the forum or gitter care should be taken to construct a useful question. Simple guidelines for posting questions to the community:
- Limit the scope of the questions.
- Briefly state what is to be accomplish.
- Give a small example embedded in the question.
- Clearly state the question in the context of the simplified problem.
- It is ok to link original code (or attach) as a reference but it should not be required to answer the question.
Example, don't post code and state: "it doesn't work, help".
Determine where the issues is and create a specific question to the problems independent of the context of the project. The easier the question is to understand and test (e.g removing extraneous information) the faster the question will be answered.
Mentors will be in a position to help dig through the project code. To get the highest probability of a timely and useful answer the above recommendation should be used when posting to the mailing-list.
This exhaustive essay on, interacting and getting questions answered by asking well-thought questions, is a good guide.
Writing Your GSoC Application
A common template is available to help bootstrap the student proposals. For more information on GSoC see the GSoC website in particular the student FAQ is a good place to start for new students and the student guide is a thorough review of the program.
Getting Started with MyHDL
The following is a list of additional examples and projects that can be used as first exercises and references:
Contributing to MyHDL Package
The MyHDL project has outlined a development process that should be followed by each participant. This includes writing enhancement proposals for projects that contribute directly to the MyHDL package. Certain project ideas are based on existing MEPs. The student proposal will be natural start to a MEP if needed.
All projects require programming in Python, previous knowledge of HDL design, and many of the MyHDL specific projects (i.e. non-cores) require experience with compilers (familiarity with the Python compiler package desirable).
MyHDL Package Project Ideas
Digital filter blocks
This project includes developing various digital filters with
MyHDL and integrating the filter-blocks with
PyFDA. The filter-blocks
will be added to the
repository. The student is encouraged to start with simple digital
filters and use the tools to verify and demonstrate the performance
of the filters. After a basic filter or two is completed it
is expected the student will complete a more complex digital filter,
examples: systolic structure, non-linear estimation filters,
modular shared-resource structures, etc.
The potential mentors for this project are:
Interface driven Ethernet core
This project involves extending the Ethernet core that was
developed in a previous GSoC to be an "interface driven"
design. The core is to be updated and extended with the
interfaces provided in the
The following example illustrates the idea of the interface driven design - the details will be developed with the student.
def example(...) glbl = Global() # clock and resets ethcfg = EthConfig() # contains all the setup info ethc = EthController() # main data interface to the eth # In this example, there are three blocks that are interfacing # with the Ethernet controller. b1 = ethc.get_branch() pkt1_inst = packet_type_a_handler(...) b2 = ethc.get_branch() pkt2_inst = packet_type_b_handler(...) b3 = ethc.get_branch() pkt3_inst = packet_type_c_handler(...) eth_inst = eth_core(glbl, ethc, ethcfg) # get the arbitration logic, handles arb_inst = ethc.arbitrate()
It is desirable, but not required, that the student have a development board with an tri-mode (10/100/1000) Ethernet phy.