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MyHDL Project Introduction

MyHDL is a Python package that extends Python as a hardware description language (HDL). MyHDL empowers implementation of complex digital circuits that can be targeted towards ASIC and FPGA technologies.

Jan Decaluwe is the creator and BDFL. The MyHDL project has been around for many years and has had many successes bringing a modern and software influenced approach to HDL development. MyHDL has been used for various FPGA projects and numerous ASIC projects 1.

The following are good starting points to learn more about MyHDL:

MyHDL Community

The MyHDL forum and the myhdl gitter channel can be used to interact with the MyHDL community. Most questions can be answered in one of these two outlets.

Questions can also be posted to:

The gitter channel is informal and typically a question will be part of a time-limited conversation. On the forum more users/developers will have a chance to comment on the question and the question will receive more feedback over time.

Before a question is posted to the forum or gitter care should be taken to construct a useful question. Simple guidelines for posting questions to the community:

  1. Limit the scope of the questions.
  2. Briefly state what is to be accomplish.
  3. Give a small example embedded in the question.
  4. Clearly state the question in the context of the simplified problem.
  5. It is ok to link original code (or attach) as a reference but it should not be required to answer the question.

Example, don't post code and state: "it doesn't work, help".
Determine where the issues is and create a specific question to the problems independent of the context of the project. The easier the question is to understand and test (e.g removing extraneous information) the faster the question will be answered.

Mentors will be in a position to help dig through the project code. To get the highest probability of a timely and useful answer the above recommendation should be used when posting to the mailing-list.

This exhaustive essay on, interacting and getting questions answered by asking well-thought questions, is a good guide.

Writing Your GSoC Application

A common template is available to help bootstrap the student proposals. For more information on GSoC see the GSoC website in particular the student FAQ is a good place to start for new students and the student guide is a thorough review of the program.

Getting Started with MyHDL

Using MyHDL

The MyHDL manual outlines how to design digital circuits with MyHDL. MyHDL installation instructions thoroughly cover installing the MyHDL package.

The following is a list of additional examples and projects that can be used as first exercises and references:

Contributing to MyHDL Package

The MyHDL project has outlined a development process that should be followed by each participant. This includes writing enhancement proposals for projects that contribute directly to the MyHDL package. Certain project ideas are based on existing MEPs. The student proposal will be natural start to a MEP if needed.

Project Ideas

All projects require programming in Python, previous knowledge of HDL design, and many of the MyHDL specific projects (i.e. non-cores) require experience with compilers (familiarity with the Python compiler package desirable).

The MyHDL package uses the LGPL license, all work submitted to the MyHDL package will be LGPL.

MyHDL Package Project Ideas

Fixed-point compiler

This project will develop the backend compiler for the proposed fixbv type. The fixbv has been proposed in MEP111. This project requires extensive compiler experience and familiarity with the Python compiler packages. Potential candidates will be required to complete a pull-request related to the backend conversion before being considered for the project.

The potential mentors for this project are:

  1. Christopher L. Felton, cfelton on IRC, @FeltonChris on twitter, and @cfelton on github

State-machine conversion enhancements

With MyHDL there are many benefits implementing state-machines but this can be enhanced additional. This project will implement features to support efficient and increased readability in state-machines especially in the case of using interfaces as the control signals.

The potential mentors for this project are:

  1. Christopher L. Felton, cfelton on IRC, @FeltonChris on twitter, and @cfelton on github
  2. Keerthan Jaic

Converter implemented in RedBaron

This is an exploratory project that will implement subset of the MyHDL conversion with RedBaron and explore feature enhancement like loop unrolling. This project will start by showing feasibility by implementing current MyHDL features defined by the LRM

  1. Henry Gomersall

FIRRTL conversoin support

Students interested in this project should comment on the the discourse thread.

This is an exploratory project that will explore using FIRRTL as a IR in MyHDL. The benefit would be using the tools in FIRRTL.

  1. Keerthan Jaic

Cosimulaton improvements

Students interested in this project should comment on the the discourse thread.

This project is an exploratory project and will investigate enhancing the cosimulaiton interface by implementing a new VPI module in Rust.

  1. Keerthan Jaic

All things waveform viewing

This is a core development and peripheral project that will work to increase tracing and waveform viewing in MyHDL. The main goals are to create an efficient waveform viewing with matplotlib and embedded the traced waveforms in jupyter notebooks. This has been prototyped but needs to be extended and needs to be more efficient. In addition, the student will explore direct FST support, the MyHDL simulator will trace directly to FST binary format instead of only support VCD.

  1. Keerthan Jaic
  2. Christopher L. Felton, cfelton on IRC, @FeltonChris on twitter, and @cfelton on github

Reduce the amount of global state used by MyHDL

MyHDL uses global variables in many places. Most notably, in the Simulation module. This is a bad idea for various reasons. The main goal of this project is to document and reduce the number of global variables used by MyHDL.

Please consult the discussion of the following rejected PR as a starting point.

  1. Keerthan Jaic

Potential Mentors