MyHDL Project Introduction

MyHDL is a Python package that extends Python as a hardware description language (HDL). MyHDL empowers implementation of complex digital circuits that can be targeted towards ASIC and FPGA technologies.

Jan Decaluwe is the creator and BDFL. The MyHDL project has been around for many years and has had many successes bringing a modern and software influenced approach to HDL development. MyHDL has been used for various FPGA projects and numerous ASIC projects 1.

The following are good starting points to learn more about MyHDL:

MyHDL Community

The MyHDL mailing-list and the #myhdl IRC channel on Freenode can be used to interact with the MyHDL community. Most questions can be answered in one of these two outlets. There is also a MyHDL tag on stackoverflow.

The IRC channel is informal and typically a question will be part of a time-limited conversation. On the mailing-list more users/developers will have a chance to comment on the question and the question will receive more feedback over time.

Before a question is posted to the mailing-list care should be taken to construct a useful question. Simple guidelines for questions on the mailing-list:

  1. Limit the scope of the questions.
  2. Briefly state what is to be accomplish.
  3. Give a small example embedded in the question.
  4. Clearly state the question in the context of the simplified problem.
  5. It is ok to link original code (or attach) as a reference but it should not be required to answer the question.

Example, don't post code and state: "it doesn't work, help".
Determine where the issues is and create a specific question to the problems independent of the context of the project. The easier the question is to understand and test (e.g removing extraneous information) the faster the question will be answered.

Mentors will be in a position to help dig through the project code. To get the highest probability of a timely and useful answer the above recommendation should be used when posting to the mailing-list.

This exhaustive essay on, interacting and getting questions answered by asking well-thought questions, is a good guide.

Writing Your Application

A common template is available to help bootstrap the student proposals. For more information on GSoC see the GSoC website in particular the student FAQ is a good place to start for new students and the student guide is a thorough review of the program.

Getting Started with MyHDL

Using MyHDL

The MyHDL manual outlines how to design digital circuits with MyHDL. MyHDL installation instructions throughly cover installing the MyHDL package.

The following is a list of additional examples and projects that can be used as first exercises and references:

Contributing to MyHDL Package

The MyHDL project has outlined a development process that should be followed by each participant. This includes writing enhancement proposals for projects that contribute directly to the MyHDL package. Certain project ideas are based on existing MEPs. The student proposal will be natural start to a MEP if needed.

The cores developed with MyHDL are intended to be incorporated into a single repository 3 at the end of the project.

Project Ideas

The project ideas fall into two categories:

  1. Enhancements to the MyHDL package.
  2. Implementing cores with MyHDL.

All projects require programming in Python.

The MyHDL package uses the LGPL license, all work submitted to the MyHDL package will be LGPL.

MyHDL Package Project Ideas

Refactor Conversion Code

This project will involve refactoring the conversion such that code can be shared between conversion utilities.

This project requires knowledge of compilers and the Python compiler support and packages. This is an advanced project that will support the overall MyHDL conversion code structure, reusability, and comprehension.

Potential mentors:

. Christopher Felton, cfelton* on IRC, @FeltonChris on twitter, and @cfelton on github

General Hierarchy Analyzer

This development is intended to have a single hierarchy analyzer. This analyzers will use the common components from the rest of the conversion code and provide additional reusable components. This would also support MEP110.

This project requires knowledge of compilers and the Python compiler support and packages. This is an advanced project that will support the overall MyHDL conversion code structure, reusability, and comprehension.

Potential mentor(s):

. Oscar Diaz, tbd* on IRC and @dargor0 on github

Cosimulation Signal Extraction

It is possible through the foriegn language interfaces (VPI/DPI) to extract all the signals in from the Cosimuation simulator and build a dict or object on the Python side. Performing this action will simplify and automate connecting a Python/MyHDL verification environment to a Verilog/VHDL simulation.

This project will require a student to investigate the MyHDL Cosimulation and research the simulator foriegn-language-interfaces, in particular VPI and/or DPI for Verilog Cosimulations and VHPI for VHDL simulations (note Cosimulation with VHDL is not currently possible due to the lack of open-source simulators with a complete VHPI or other FLI). This task requires moderate skill level, general simulator knolwedge and will require Python and C coding. This work will mainly be completed with the Icarus Verilog or CVC simulators.

2D List-of-Signal Conversion

The MyHDL conversion currently handles converting a list-of-signals. But it is ofthen desired to use multi-dimension (list of lists) to structure data and/or signals. This project will involve exploring the list-of-signal conversion, proposing an architecture for multi-dimension conversion, a complete set of tests, and an implementation for the conversion.

Initial Value Support

Most synthesis tools (e.g FPGA Quartus, xst, Vivado) support initial condition mechanisms. This project would involve complete investigation which synthesis tools support intial conditions (variable, Signal, and RAM). Once the supported methods are determined a proposal and implemenation for initial conditions will be developed.

MyHDL Cores Project Ideas

The following projects are the development and/or ports of common building blocks used in many complex digital systems. These are not intended to be straight ports. They are intended to be designed in the MyHDL philosophy bringing many software concepts to hardware design and creating modular and scalable cores.

Gigabit Ethernet MAC

This project involves porting a GEMAC core to MyHDL. The GEMAC is typically used to stream data in and out of an FPGA versus the lower throughput in common IO Ethernet connections.

The project has a reference Verilog design and a test framework.
The test framework will be used to validate the core and encourage test driven design.

Like all the cores being implemented in MyHDL these cores should be designed bus agnostic. The GEMAC requires in/out data-path and optional memory-map interface. If the optional memory-map interface is not included the default configuration should easily be set during instantiation. The core should support many different standards for the different type if interfaces. The following is an example that shows how the interfaces are past to the core:

mmbus = AvalonMM(...)
databus = AvalonST(...)
geth = m_eth_lite(glbl, databus, mmbus)

mmbus = Wishbone(...)
databus = FIFOBus(...)
geth = m_eth_lite(glbl, databus, mmbus)

By using the interfaces and passing the interface types the core become truly modular and scalable.

This project requires digital circuit familiarity, ability to read and understand Verilog and Python. Knowledge of Ethernet standards and protocols will be useful.

Hardware testing is not an explicit requirement of this project but would be a great addition.

The potential mentors for this project are:

  1. Guy Eschemann, tbd on IRC, @geschema on twitter, and @geschema on github

HDMI Source / Sink

An HDMI controller sources and sinks a video stream. The core performs the required encoding and decoding to an HDMI link. It also provides a mechanism to "query" the connected device.

The project has a reference Verilog design and a test framework.
The test framework will be used to validate the core and encourage test driven design.

This project requires digital circuit familiarity, ability to read and understand Verilog, and Python.

The potential mentors for this project are:

SDRAM Controller

The project has a reference VHDL design to port and a test framework.
The test framework will be used to validate the core and encourage test driven design. The core port/development should also include the embedded memory test Although not explicitly required for the project it would be beneficial if the core was tested on hardware.

As the general cores project description indicated, this is not a simple port. The generated core should support the functionality of the reference design but the core should also explore creating a core that is modular and scalable. It should be explored if a single controller can be designed to support multiple interfaces and standards. This typically involves advanced usage of elaboration code.

This project requires digital circuit familiarity, ability to read and understand Verilog, and Python. Knowledge of external memory types and memory controller desired but not required.

The potential mentors:

JPEG Encoder

This project is the design and/or port of a JPEG encoder. Same as the other core projects, the goal is to demonstrate a modern HDL implementation usign MyHDL. Hardware versions of JPEG encoders are common for (basic) video compression. The reference core and test framework is the starting point for this project. This project should convert / implement one component at a time. The following is a suggested order of implementation:

* RGB to YCBCR conversion
* 2D DCT
* Quantizer
* Huffman module
* Misc: FIFOs, etc.
* Top-level

This project requires digital circuit familiarity, ability to read and understand Verilog, and Python.

Leros tiny processor

Leros is a tiny soft-core processor optimized for low-cost FPGAs , written in technology-agnostic VHDL. The architecture is a pipelined 16-bit accumulator, designed with a balance of logic resources and on-chip memory.

Tiny processors applications include:

  • Implement complex states machines with a tiny processor and a tiny assembler program.
  • Implement intelligent peripheral device for auxiliary functions.
  • Many-core applications and massive parallel algorithms.

This project has the architecture documentation and a reference VHDL design to port. The project will include not only the port but also the test framework and testbenches in MyHDL to use test driven design features. A user guide for the processor core is also planned in the project.

Test on real hardware is desirable, in order to compare logic resources usage and real performance of both MyHDL and VHDL implementations.

This project requires digital circuit familiarity and experience with VHDL. A background on computer architecture and microcontrollers is desired but not required.

Other Cores

There are an unlimited number of cores that can be implemented with MyHDL. Any core can be proposed but will not have the existing support as above project ideas. If a student has a particular core they would like to port to or implement with MyHDL, start a conversation with the community and generate a proposal.

Potential Mentors