0.6 has been released.
- RAM support using array types
- operators with signed operands
- augmented operators
- user-defined VHDL support
toVerilogso that it can work with the new verification method also. In particular,
- write conversion verification test benches for some cookbook examples
- include date/tool info in conversion output
if __debug__functionality with new verification capabilities
- encoding attributes to enumeration types
- use a package in a separate file for general VHDL output code
Find a good solution to avoid name clashes. In the Verilog output, I relied on using
_as a prefix, but because VHDL doesn't allow this, and I want a general solution, this needs to change.
Find a good solution to avoid name clashes with Verilog and VHDL keywords.
Rom inference support
Currently, ROMs are inferred from case statements, as in Verilog. Users and synthesis tools may prefer arrays of integers. Feedback welcome.
User-defined VHDL code
It is straightforward to support the
__toVHDL__ attribute for
user-defined VHDL, similar to the Verilog solution. This may not be sufficient
however, because VHDL requires instantiated components to be declared in the
code. We may have to add a way to add such user-defined declarations.